2.2. 时钟信号
本节介绍了F-Tile Ethernet Multirate IP core所需要的时钟连接和时钟信号。
Ethernet Multirate IP core对一个重配置组中的所有端口使用o_clk_pll通用系统PLL时钟。
i_reconfig_clk输入是用于一个重配置组中 Avalon 存储器映射接口的所有端口通用时钟。您必须在F-Tile Dynamic Reconfiguration IP core和所有面向一个特定tile的F-Tile Ethernet Multirate IP core实例中使用相同的重配置时钟。
您必须完成以下时钟连接：
- i_clk_ref和i_clk_sys时钟驱动IP core。
- 输出时钟o_clk_pll驱动i_clk_rx以及i_clk_tx输入信号。
图 3. 典型的时钟连接下图显示了Ethernet Multirate IP core及其相关的时钟信号。
| Signal Name | Number of Ports | I/O Direction | Description |
|---|---|---|---|
| Clock Inputs | |||
| i_clk_tx | 1, 2, or 4 | Input | TX datapath clock This clock drives the active TX interface for the port.
This clock source is:
|
| i_clk_rx | 1, 2, or 4 | Input | RX datapath clock This clock drives the active RX interface for the port.
This clock source is:
|
| i_reconfig_clk | 1, 2, or 4 | Input | Avalon 存储器映射接口 reconfiguration clock The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency. When PTP is enabled, the i_reconfig_clk frequency supports the range of 100 to 250 MHz. |
| i_clk_ref | 1, 2, or 4 | Input | PMA reference clock
F-Tile Reference and System PLL Clock Intel® FPGA IP drives this clock.
The clock source depends on the PMA selection.
Unless the Custom cadence parameter is enabled, the clock must be PPM matched to the i_clk_sys clock. |
| i_clk_sys | 1, 2, or 4 | Input | Ethernet system clock F-Tile Reference and System PLL Clocks Intel® FPGA IP drives this clock.
Unless Custom cadence parameter is enabled, the clock frequency depends on the FEC type:
You must specify this frequency in the F-Tile Ethernet Multirate Intel® FPGA IP System PLL frequency IP parameter and in the F-Tile Reference and System PLL Clocks Intel® FPGA IP Mode of system PLL IP parameter.
注： The i_clk_sys is a virtual signal. In simulation, the signal displays as 0.
Connect to the out_systempll_clk_i signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP. |
| Clock Outputs | |||
| o_clk_pll | 1, 2, or 4 | Output | System PLL clock Clock derived from the F-Tile System PLL associated with the Ethernet IP port. The o_clk_pll frequency is equal to PLL frequency divided by 2. The following shows the o_clk_pll frequency unless you enabled custom system PLL frequency.
Supports the following frequencies:
|
| Signal Name | Number of Ports | I/O Direction | Description |
|---|---|---|---|
| o_p0_clk_tx_div | 1, 2, or 4 | Output |
Supports the following frequencies:
Clock recovered from the TX SERDES rate divided by either 33/66/68, depending on the FEC mode and Ethernet mode parameters. The o_clk_tx_div is equal to:
|
| o_p0_clk_rec_div64 | 1, 2, or 4 | Output |
Supports the following frequencies:
Clock derived from RX recovered clock, divided by 64. |
| o_p0_clk_rec_div | 1, 2, or 4 | Output |
Supports the following frequencies:
Clock derived from the RX recovered clock divided by either 33/66/68, depending on the FEC mode parameter. The o_clk_rec_div is equal to:
|
| o_p1_clk_tx_div | 2 or 4 | Output | Same as the o_p0_clk_tx_div signal description |
| o_p1_clk_rec_div64 | 2 or 4 | Output | Same as the o_p0_clk_rec_div64 signal description |
| o_p1_clk_rec_div | 2 or 4 | Output | Same as the o_p0_clk_rec_div signal description |
| o_p2_clk_tx_div | 4 | Output | Same as the o_p0_clk_tx_div signal description |
| o_p2_clk_rec_div64 | 4 | Output | Same as the o_p0_clk_rec_div64 signal description |
| o_p2_clk_rec_div | 4 | Output | Same as the o_p0_clk_rec_div signal description |
| o_p3_clk_tx_div | 4 | Output | Same as the o_p0_clk_tx_div signal description |
| o_p3_clk_rec_div64 | 4 | Output | Same as the o_p0_clk_rec_div64 signal description |
| o_p3_clk_rec_div | 4 | Output | Same as the o_p0_clk_rec_div signal description |
由于重配置组中的所有端口都共享同一系统PLL时钟，因此锁定的状态输出是常见的。收发器PLL和RX CDR时钟信号是特定于端口的，取决于Number of Ports设置。
| Signal Name | Number of Ports | I/O Direction | Description |
|---|---|---|---|
| o_sys_pll_locked | 1, 2, or 4 | Output | Indicates the locked system PLL. Do not use the o_clk_pll clock until the o_sys_pll_locked clock is high. |
| o_p0_tx_pll_locked | 1, 2, or 4 | Output | Indicates the TX PLL driving clock signal from the core is locked. Do not use the o_clk_tx_div clock until the o_p0_tx_pll_locked clock is high. |
| o_p0_cdr_lock | 1, 2, or 4 | Output | Indicates that the recovered clocks are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p0_cdr_lock clock is high. |
| o_p1_tx_pll_locked | 2 or 4 | Output | If you set the number of ports to 2 or 4, indicates the TX PLL driving clock signal from the core port1 is locked. Do not use the o_clk_tx_div clock until the o_p1_tx_pll_locked clock is high. |
| o_p1_cdr_lock | 2 or 4 | Output | If you set the number of ports to 2 or 4, indicates that the recovered clocks from port 1 are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p1_cdr_lock clock is high. |
| o_p2_tx_pll_locked | 4 | Output | If you set the number of ports to 4, indicates the TX PLL driving clock signal from the core port2 is locked. Do not use the o_clk_tx_div clock until the o_p2_tx_pll_locked clock is high. |
| o_p2_cdr_lock | 4 | Output | If you set the number of ports to 4, indicates that the recovered clocks from port 2 are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p2_cdr_lock clock is high. |
| o_p3_tx_pll_locked | 4 | Output | If you set the number of ports to 4, indicates the TX PLL driving clock signal from the core port3 is locked. Do not use the o_clk_tx_div clock until the o_p3_tx_pll_locked clock is high. |
| o_p3_cdr_lock | 4 | Output | If you set the number of ports to 4, indicates that the recovered clocks from port 3 are locked to data. Do not use the o_clk_rec_div64 or o_clk_rec_div clocks until the o_p3_cdr_lock clock is high. |