F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南

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ID 683287
日期 12/13/2021
Public
文档目录
文档目录 x
1. 关于F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南 2. 快速入门指南 3. F-Tile Serial Lite IV设计实例详细描述 4. F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南存档 5. F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南文档修订历史
2. 快速入门指南 x
2.1. 设计实例结构框图 2.2. 软件和硬件要求 2.3. 生成设计 2.4. 编译和仿真设计 2.5. 编译和测试设计
2.3. 生成设计 x
2.3.1. 设计实例参数 2.3.2. 目录结构
3. F-Tile Serial Lite IV设计实例详细描述 x
3.1. 功能特性 3.2. 设计实例组件 3.3. 仿真 3.4. 硬件测试 3.5. 错误处理 3.6. 链路调试顺序 3.7. F-Tile Serial Lite IV IP工具包
3.2. 设计实例组件 x
3.2.1. 流量发生器 3.2.2. 流量检查器 3.2.3. DCFIFO
3.3. 仿真 x
3.3.1. 基础模式的仿真结果 3.3.2. 全模式的仿真结果 全传输模式下使能RS-FEC的PAM4的仿真结果 全传输模式下未使能RS-FEC的NRZ的仿真结果
3.7. F-Tile Serial Lite IV IP工具包 x
3.7.1. 设置和运行工具包 3.7.2. 工具包GUI设置
1. 关于F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南
2. 快速入门指南
3. F-Tile Serial Lite IV设计实例详细描述
4. F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南存档
5. F-Tile Serial Lite IV Intel® FPGA IP设计实例用户指南文档修订历史

3.3.2. 全模式的仿真结果

全模式或者数据包传输（packet transfer）模式下，流量发生器以随机次数的突发生成10,000个字，并在TX和RX链路建立后发送到IP。随后这些字被环回到RX MAC。RX MAC将突发发送到流量检查器进行数据验证。您可以在仿真结果中找到以下信息：
  • TX和RX链路状态
  • IP的配置设置
  • 每突发发送的样本字数
  • 测试结果，以及传输的总字数、突发数和链路延迟值

以下是每个设计实例变体的仿真结果示例。

全传输模式下使能RS-FEC的PAM4的仿真结果

注： 使能RS-FEC的NRZ变体具有与使能RS-FEC 的PAM4变体相似的仿真结果。 
#    Waiting for TX Link Up
# 
#    Phy TX Lanes Stable asserted at time 354081776
# 
#    Phy EHIP ready asserted at time 475222181
# 
#    TX link_up asserted at time 475228320
#       TX user_clock frequency              = 3.731343e+02 MHz
#       RX user_clock frequency              = 3.731343e+02 MHz
#    
#    *************************************** Test Started *************************************
#    
#    Tests started at time 475239040
#    
#    LANES                         = 4
#    
#    Streaming Mode                = FULL
#    
#    SRL4 Align Period             = 128
#    
#    RSFEC Enable                  = 1
#    
#    PER LANE CRC ENABLE Enable    = 0
#    
#    ******************************* Data Forwarding Test Initialize *****************************
#    
#    Waiting for RX Link Up
# 
#    Phy block lock asserted at time 495699771
# 
#    Phy RX PCS Ready asserted at time 495731094
# 
#    RX link_up asserted at time 495786600
#    
#    ******************************* Data Forwarding Test Started *****************************
#    
#    Test Mode:            Burst
#    User Stall Insertion: Disabled
#    
# 
#    Traffic Generator: 98 sample burst started at time 495797320
# 
#    Traffic Generator: 17 sample burst started at time 496110880
.
.
.
#    Traffic Checker: Burst start descriptor read at time 534212440
#                     Sync value 242
#                     Sample number 9907
# 
#    Traffic Checker: Burst end descriptor read at time 534534040
#                     Inter-burst interval 7
#                     Empty value 0
#                     Sample number 10000
#    
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 534810080
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 196
#    
#    Random number generator seed   = 1756255697
#    
#    Link Latency                   = 0 ns
#    
#    *************************************** Test Passed **************************************

全传输模式下未使能RS-FEC的NRZ的仿真结果

#    Waiting for TX Link Up
# 
#    Phy TX Lanes Stable asserted at time 3007624010
# 
#    Phy EHIP ready asserted at time 4397012810
# 
#    TX link_up asserted at time 4397112640
#       TX user_clock frequency              = 3.511236e+02 MHz
#       RX user_clock frequency              = 3.511236e+02 MHz
#    
#    *************************************** Test Started *************************************
#    
#    Tests started at time 4397226560
#    
#    LANES                         = 2
#    
#    Streaming Mode                = FULL
#    
#    SRL4 Align Period             = 128
#    
#    RSFEC Enable                  = 0
#    
#    PER LANE CRC ENABLE Enable    = 0
#    
#    ******************************* Data Forwarding Test Initialize *****************************
#    
#    Waiting for RX Link Up
# 
#    Phy block lock asserted at time 4423739210
# 
#    Phy RX PCS Ready asserted at time 4424123210
# 
#    RX link_up asserted at time 4425564160
#    
#    ******************************* Data Forwarding Test Started *****************************
#    
#    Test Mode:            Continuous
#    User Stall Insertion: Disabled
#    
# 
#    Traffic Generator: 10000 sample continuous transfer started at time 4425678080
# 
#    Traffic Checker: Burst start descriptor read at time 4428412160
#                     Sync value 125
#                     Sample number 1
# 
#    Traffic Checker: Burst end descriptor read at time 4811468160
#                     Inter-burst interval 0
#                     Empty value 0
#                     Sample number 10000
#    
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 4814401600
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 1
#    
#    Random number generator seed   = 1221861777
#    
#    Link Latency                   = 2900 ns
#    
#    *************************************** Test Passed **************************************
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