Intel® Quartus® Prime Standard Edition用户指南: 设计优化

ID 683230
日期 11/12/2018
Public
文档目录

2. 优化设计网表

本章节说明如何使用 Intel® Quartus® Prime Netlist Viewer分析和调试您的设计。

As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize, and constrain your design is critical. With today’s advanced designs, several design engineers are involved in coding and synthesizing different design blocks, making it difficult to analyze and debug the design. The Intel® Quartus® Prime RTL Viewer, State Machine Viewer, and Technology Map Viewer provide powerful ways to view your initial and fully mapped synthesis results during the debugging, optimization, and constraint entry processes.