仅对英特尔可见 — GUID: mwh1410471208444
Ixiasoft
仅对英特尔可见 — GUID: mwh1410471208444
Ixiasoft
3.4.3.1. 使用Timing Analyzer显示Path Report
如果任何时钟域有失败路径(在Report窗中以红色突出显示),右键点击Clocks Summary窗中罗列的时钟名称并选择Report Timing了解详细信息。
在Summary of Paths选项卡中选择路径时,路径详情窗显示所有路径信息。Extra Fitter Information选项卡提供物理器件上路径位置的直观表示。从而透露时序失败是否与距离相关,是由于源和目标节点太过靠近或相距甚远。
Data Path选项卡显示Data Arrival Path和Data Required Path。可通过增量信息确定导致时序违规的最主要路径段。Waveform选项卡显示时间域中的信号,并描述达到数据和所需数据间的时间裕量。
The RTL Viewer or Technology Map Viewer provide schematic (gate-level or technology-mapped) representations of the design netlist, and can help you to assess which areas in a design can benefit from reducing the number of logic levels. To locate a timing path in one of the viewers, right-click a path in the timing report, point to Locate, and select either Locate in RTL Viewer or Locate in Technology Map Viewer. You can also investigate the physical layout of a path in detail with the Chip Planner.