Intel® Quartus® Prime Pro Edition用户指南: 入门

ID 683463
日期 9/28/2020
Public
文档目录

4.11.2. 顶层 VHDL模块实例

顶层模块中的VHDL ALTFP_MULT通过One Input连接Multiplexer。
library ieee; use ieee.std_logic_1164.all; library altera_mf; use altera_mf.altera_mf_components.all; entity MF_top is port (clock, sel : in std_logic; a, b, datab : in std_logic_vector(31 downto 0); result : out std_logic_vector(31 downto 0)); end entity; architecture arch_MF_top of MF_top is signal wire_dataa : std_logic_vector(31 downto 0); begin wire_dataa <= a when (sel = '1') else b; inst1 : altfp_mult generic map ( pipeline => 11, width_exp => 8, width_man => 23, exception_handling => "no") port map ( dataa => wire_dataa, datab => datab, clock => clock, result => result); end arch_MF_top;