Enclustra is a dynamic, innovative and successful FPGA design services and solutions company located in Zürich, Switzerland. Enclustra provides services covering the whole range of FPGA-based system development: From high-speed hardware or HDL firmware through to embedded software, from specification and implementation through to prototype production. Enclustra also develops and markets highly-integrated FPGA modules, SoMs and FPGA-optimized IP cores. By specializing in forward-looking FPGA technology, and with a broad application knowledge, Enclustra can offer ideal solutions at minimal expense in many areas.
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The Mercury+ SA2 system-on-chip (SoC) module combines Intel's Cyclone V ARM Processor-based SoC FPGA with fast DDR3L SDRAM, eMMC flash, quad SPI flash, a Gigabit Ethernet PHY, dual Fast Ethernet PHYs and an RTC and thus forms a high-performance embedded processing solution, combining the flexibility of a CPU system with the raw, real-time parallel processing power of an FPGA.
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The Mercury SA1 system-on-chip (SoC) module combines Intel's Cyclone V ARM Processor-based SoC FPGA with fast DDR3 SDRAM, eMMC flash, quad SPI flash, a Gigabit Ethernet PHY and an RTC and thus forms a high-performance embedded processing solution, combining the flexibility of a CPU system with the raw, real-time parallel processing power of an FPGA.
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The Mars MA3 system-on-chip (SoC) module combines the Intel® Cyclone® V SoC device with fast DDR3L SDRAM, quad SPI flash, a Gigabit Ethernet and a Fast Ethernet PHY as well as an RTC and thus forms a complete and powerful embedded processing system. The SO-DIMM form factor allows space-saving hardware designs as well as quick and simple integration of the module into the target application. The Mars MA3 SoC module reduces development effort, redesign risk and improves time-to-market for your embedded system.
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The Mercury CA1 module offers high-performance yet low cost Intel Cyclone IV FPGAs in conjunction with standard interfaces like USB 2.0 and Gigabit Ethernet. With its powerful standard interfaces, the many LVDS capable I/Os, the large DDR2 SDRAM and the many hardware multipliers it is equally suited for digital signal processing, networking, high-speed I/O as well as SoPC applications utilizing the Intel Nios® II soft processor. The Mercury CA1 FPGA board reduces development effort, redesign risk and improves time-to-market.
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The Mercury+ AA1 system-on-chip (SoC) module combines Intel's Arria 10 ARM Processor-based SoC FPGA with fast DDR4 ECC SDRAM, eMMC flash, quad SPI flash, Gigabit Ethernet PHY and an RTC and thus forms a high-performance embedded processing solution, combining the flexibility of a CPU system with the raw, real-time parallel processing power of an FPGA.
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High-performance FPGA/SoC motion control – supporting DC, BLDC and stepper motors Enclustra's Universal Drive Controller is a highly optimized IP solution, featuring implementations of commonly-used motor control algorithms for position, velocity and current control, as well as all required interfaces to the power electronics. A simple and portable C programming API allows easy access to all features from software. Features and benefits: Control up to 8 motors simultaneously Control loop update rates of up to 200 kHz Supports BLDC, DC and stepper motors Features field-oriented control for BLDC motors Fully autonomous event handling Position control and trajectory planner Flexibility is key Full support for custom current, position and velocity measurement circuits Specify which controls loops are autonomous and which are implemented in software Integration and ease of use C programming API to access all features Full integration with Intel® tools Reference designs available for all motor types Evaluation ƒ A free IP evaluation license including reference design and example application is available ƒ Start with a spinning motor using a quick-start kit including an SoC module, base board, power electronics and motor.
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The UDP/IP/Ethernet IP Core implements a versatile communication solution that allows data transfer via Ethernet using the UDP protocol without the need of a CPU or Ethernet stack. It provides easy to use FIFO/AXI-Stream interfaces on the FPGA side and connects to any Ethernet PHY. Optionally, non-UDP communication is supported for management and configuration as well. The IP core is able to operate at full 1 Gbit/sec wire speed. 100 Mbit/sec and 10 Mbit/sec operation is also supported.