Rambus makes industry-leading chips and IP that advance data center connectivity and solve the bottleneck between memory and processing. The ongoing shift to the cloud, along with the widespread advancement of AI across data center, 5G, automotive and IoT, has led to an exponential growth in data usage and tremendous demands on data infrastructure. Creating fast and safe connections, both in and across systems, remains one of the most mission-critical design challenges limiting performance in advanced hardware. Rambus is ideally positioned to address this challenge as an industry pioneer with over 30 years of advanced semiconductor interconnect experience moving and protecting data. We are a leader in high-performance memory subsystems, providing chips, IP and innovations that maximize the performance and security in data-intensive systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data transfer speed and trust. Rambus products and innovations deliver the increased bandwidth, capacity and security required to usher in a new era of data center architectures and drive ever-greater end-user experiences.
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Key Features: VESA® Display Stream Compression (DSC) 1.2b compliant, supports all DSC 1.2b mandatory and optional encoding mechanisms, backward compatible to DSC v1.1. Configurable maximum display resolution up to 8K (FUHD) • 8, 10, 12 bits per video component, YCbCr and RGB video output format • 4:4:4, 4:2:2, and 4:2:0 native coding , resilient to bitstream corruption, 3 pixels / clock internal processing architecture in 4:4:4 • 6 pixels / clock internal processing architecture in 4:2:2 and 4:2:0. Parameterizable number of parallel slice decoder instances(1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used. Automatic run time configuration of the number of parallel slice decoder instances in use • Support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® platform designer tool. Avalon memory-mapped interface for register access, PPS 128 bytes block decoding, Compliant solution for DisplayPort 1.4 or HDMI 2.1o compatibility for slices per line requirements. Supports flexible usage models and design architecture (inline decoding or panel frame buffer decoding).
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Key Features: VESA® Display Stream Compression (DSC) 1.2b compliant, supports all DSC 1.2b mandatory and optional encoding mechanisms, backward compatible to DSC v1.1. Configurable maximum display resolution up to 8K (FUHD). 8, 10, 12 bits per video component YCbCr and RGB video output format 4:4:4, 4:2:2, and 4:2:0 native coding, 1 pixel / clock internal processing architecture in 4:4:4, 2 pixels / clock internal processing architecture in 4:2:2 and 4:2:0 .Parameterizable number of parallel slice encoder instances (1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used, support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® plaform designer tool. Avalon memory-mapped interface for register access. Compliant solution for DisplayPort 1.4™ or HDMI® 2.1o Compatibility for slices per line requirements when using a frame buffer ,supports flexible usage models and design architecture.
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Key Features: VESA® Display Compression-M (VDC-M) 1.2 compliant. Supports all VDC-M encoding mechanisms o BP, transform, MPP, MPP fallback, and BP skip o Flatness detection and signaling. Configurable maximum display resolution of up to 16Kx16Ko Typical 4K (4096x2160), 5K UHD+, and 8K UHD supported, configurable compressed bit rate, in increments of 1/16 bitsper pixel (bpp) 8, 10, or 12 bits per component video 4:4:4 sampling for RGB video input format 4:4:4, 4:2:2, and 4:2:0 sampling for YCbCr video input formats Pixel throughput of two (2) pixels per clock per hard slice encoder. Parameterizable number of parallel slice encoder instances(1,2, 4, or 8) to adapt to the capability of the technology and target display resolutions used. Logical slice encoding (2 soft slices) in each physical encoder (hard slice), support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® platform designer tool, Avalon memory-mapped interface for register access. Compliant solution for MIPI® DSI-2SM v1.1. Supports flexible usage models and design architecture.
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The Rambus PCI Express® (PCIe) 4.0 Controller with AXI is a configurable and scalable design for ASIC and FPGA implementations. It is backward compatible to PCIe 3.1/3.0, and compatible with version 4.x of PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ protocol specification.
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The Rambus PCI Express® (PCIe) 3.1 Controller is designed to achieve maximum PCIe 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. The controller delivers high-bandwidth and low latency connectivity for demanding applications in data center, edge and graphics.
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The Rambus PCI Express® (PCIe) 5.0 Controller with AXI is a configurable and scalable design for ASIC and FPGA implementations. It is backward compatible to PCIe 4.0 and 3.1/3.0, and compatible with version 5.x of PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ Protocol Specification.
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The Rambus PCI Express® (PCIe) 3.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. It supports the PCI Express 3.1/3.0 specifications, as well as the PHY Interface for PCI Express (PIPE) specification and the AMBA® AXI™ protocol specification.
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The Rambus PCI Express® (PCIe) 5.0 Controller is a configurable and scalable design for ASIC and FPGA implementations. It is backward compatible to PCIe 4.0 and 3.1/3.0, and supports version 5.x PHY Interface for PCI Express (PIPE) specification.
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The Rambus PCI Express® (PCIe) 4.0 Controller is a configurable and scalable design for ASIC and FPGA implementations. It is backward compatible to PCIe 3.1/3.0, and supports version 4.x PHY Interface for PCI Express (PIPE) specification. When combined with the Rambus PCIe 4.0 PHY, it comprises a complete PCIe 4.0 interface subsystem.
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The Rambus DSI-2 controller core is a second-generation MIPI DSI core optimized for high performance, low power and small size. The core is fully compliant with the DSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.
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The Rambus CSI-2 controller core is a second-generation MIPI CSI-2 core optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.