DPSMBUS - SMBUS & PMBUS Master/Slave controller
关于此报价
DPSMBUS is a fully-featured module based on the I2C protocol, which supports SMBus and PMBus functionalities. It can operate as a DPSMBUSM – Master and DPSMBUSS – Slave. Due to SMBus and PMBus documentation, the module meets requirements, both for SMBSDA and SMBSCK , for acceptable timing intervals. DSPMBUS module supports arbitration and clock synchronization, which is necessary for multi-master systems. The IP Core, as it’s been suggested in the SMBus documentation, has implemented a reaction on a stuck SMBSCK signal in a low state Ttimeoutmin.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 处理器和外设: 外设
- 最终客户类型:
-
企业
资源
采用的英特尔技术
英特尔® MAX® 10 FPGA
英特尔® Stratix® 10 FPGA 和 SoC FPGA
英特尔® Cyclone® 10 FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovat...
Dpsmbus - Smbus & Pmbus Master/slave Controller
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