DI2CM-FIFO - I2C Bus Interface – Master with FIFO
关于此报价
DI2CM-FIFO bridge to APB, AHB, AXI bus, this core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:a master transmitter ormaster receiver depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. The built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology-independent design that can be implemented in a variety of process technologies.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 处理器和外设: 外设
- 最终客户类型:
-
企业
资源
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Di2cm-fifo - I2c Bus Interface – Master With Fifo
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