DHDLC - HDLC/SDLC controller
关于此报价
DHDLC bridge to APB, AHB, and AXI bus, provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending and detection. And if it’s not enough, let’s just mention that DCD’s IP Core supports CRC16 and CRC32 computation. Increased system performance and reduced CPU overload are a must-be, thanks to the presence of separate receiver and transmitter FIFO buffers, maskable interrupt, and DMA interface requests. The DHDLC is a fully scalable IP Core, which makes it a perfect solution for both high-end and deeply embedded projects.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 处理器和外设: 外设
- 最终客户类型:
-
企业
采用的英特尔技术
DIGITAL CORE DESIGN
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Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and thanks to in-depth specialization and innovat...
Dhdlc - Hdlc/sdlc Controller
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