Introduction
This article looks at inline IPsec acceleration support enablement in the Data Plane Development Kit (DPDK) framework with a particular focus on the Intel® 82599 10 Gigabit Ethernet Controller series features and support.
Inline IPsec can be used to implement IPsec-aware systems that have a better latency than lookaside-assisted and accelerated hardware, providing that the algorithm supported is suitable.
This article includes background information that will highlight the differences between “lookaside” hardware acceleration for IPsec and inline IPsec (i.e., the packet flow differences and the expected differences on the application side, in performance and handling).
An example of setting up a test system, installing, and running an IPsec Gateway application will be presented.
The article assumes that the DPDK release used is 17.11 or later.
Background
The DPDK Security Library provides a framework for the management and provisioning of security protocol operations offloaded to hardware-based devices. The library defines generic APIs to create and free security sessions that can support full protocol offload as well as inline crypto operations with network interface controller (NIC) or crypto devices.
The security library, which has been included in the DPDK since release 17.11, introduces APIs and features that provide a way of adding support for the inline crypto (IPsec) acceleration already available on the Intel 82599 10 Gigabit Ethernet Controller series. The DPDK IXGBE driver was also updated with support for inline IPsec.
The Intel 82599 10 Gigabit Ethernet Controller series only supports AES-GCM 128, hence the supported protocols:
- ESP authentication only: AES-128-GMAC (128-bit key)
- ESP encryption and authentication: AES-128-GCM (128-bit key)
The IPsec Security Gateway sample application also supports this feature, which will be explained in more detail below.
Packet Flow
First, let’s look at the packet flow and handling through the system.
Figure 1.
The packet flow depicted above shows the packet-processing stages for an incoming encrypted IPsec packet. In the first case, it is processed (decrypted and/or authenticated) using the lookaside Intel® QuickAssist Technology (Intel® QAT) hardware accelerator. In the second case, it is processed using the inline IPsec hardware processing available in the Intel 82599 10 Gigabit Ethernet Controller.
As presented above, the second stage of the processing (decryption and/or authentication) is combined with the packet receive stage by the network controller itself. The DPDK application still needs to process the encapsulation and de-capsulation of the Encapsulating Security Payload (ESP) packet.
The outgoing flow is identical except for the packet direction.
Software APIs and the Sample Application
Now, let’s look at the software APIs, requirements, and usage model. We will use code excerpts from the IPsec Security Gateway sample application, simplified for clarity, and with error handling removed.
First, we need to create a security session, beginning with the following configuration:
Next, create the security session:
Then, create an RTE_FLOW_ACTION_TYPE_SECURITY flow:
With this, the configuration is complete and the Security Association (SA) is active for incoming ESP packets that match the flow created. The offload flags in the “rte_mbuf” struct will indicate if the packet was processed inline by setting the PKT_RX_SEC_OFFLOAD flag and, if any error occurred, PKT_RX_SEC_OFFLOAD_FAILED will also be set.
For outgoing packets, the programming is similar except that the offload flag PKT_TX_SEC_OFFLOAD needs to be set by the application.
Test System Setup
In addition to DPDK and the sample application, we will use Python* scapy v2.4.0 (packet generator) and pycryptodome v3.6.0 (which provides AES-GCM support) to generate clear text and encrypted packets.
Save the following as inline_ipsec.py:
The test system configuration is shown in the figure below.
Figure 2.
The configuration uses two Intel® 82599ES 10 Gigabit Ethernet Controller dual port cards connected as shown above.
In this particular configuration, card 1 ports will be assigned to the DPDK driver, port 0 BDF 06:00.0 and port 1 BDF 06:00.1. Card 0 ports will be assigned to the kernel driver, identified as enp2s0f0 and enp2s0f1. Note, in other systems the addresses and port names may be different.
Create the IPsec sample app configuration based on this data and save it as a file called inline.cfg. For example:
Then start the application as follows:
Note that the NULL crypto device is only present because the application needs a “true” crypto PMD (for legacy reasons).
Testing ESP decryption and forwarding of the decrypted packets
In order to test the application, send encrypted packets on port 1:
python inline_ipsec.py -i enp2s0f1 -s 64 -c 32 -e 1
While listening on port 0:
tcpdump -i enp2s0f0 –vvX
Decrypted packets should be observed on port 0:
The packet flow is as follows:
- ESP packet is received on port 1.
- Port 1 RX queue contains ESP packet with the payload decrypted.
- ESP decapsulation.
- Clear text packet containing decrypted payload is transmitted on port 0.
Testing ESP encryption
In order to test the application, send clear text packets on port 0:
python inline_ipsec.py -i enp2s0f0 -s 64 -c 32 -e 0
While listening on port 1:
tcpdump -i enp2s0f0 –vvX
Encrypted packets should be observed on port 1:
The packet flow is as follows:
- Clear text packet is received on port 0.
- ESP encapsulation.
- Packet is placed in the TX queue on port 1.
- Packet is encrypted by port 1 during transmission.
Conclusion
This article presented the details of the inline IPsec support available with the Intel 82599 10 Gigabit Ethernet Controller, how it works internally and how it is supported by the DPDK framework, and how to build an application that can utilize the feature.
About the Author
Radu Nicolau is a network software engineer with Intel. His work is currently focused on IPsec-related development of data plane functions and libraries. His contributions include enablement of the AES-GCM crypto algorithm in the VPP IPsec stack, IKEv2 initiator support for VPP, and inline IPsec enablement in DPDK.
"