Security requires collaboration between software and hardware. Working together, they can manage the risk from the incidental channels inherent to modern CPU microarchitecture.
Follow foundational advice for developers and system administrators to help maximize your application or system's resistance to side channels and other vulnerabilities.
Most traditional side channels—regardless of technique—can be mitigated by applying general "constant time" principles to all code that interacts with secrets.
Read about how to effectively address speculative execution in Intel processors using hardware controls and software techniques to secure code execution, limit the performance impact of mitigations, and avoid mitigation redundancies.
Processor support for certain mitigation mechanisms and features is enumerated using the CPUID instruction and architectural MSRs.
Building on the previous cryptographic implementation guidance, when implementing cryptographic algorithms, a new model-specific register (MSR) control has been added to enable data operand-independent timing for these data operand-independent timing instructions.